Before presenting the data we need to establish some conventions:

  • The opcode bits are separated in 3 octal numbers (x, y, z) where x = MSB and Z = LSB
  • The tables are categorized based on a constant value, like z = 0

X=0 and Z=0

Relative jumps and others

Mmemonicx y zHex
NOP00 000 0000x00
LD (nn),SP00 001 0000x08
STOP00 010 0000x10
JR n00 011 0000x18
JR NZ,n00 100 0000x20
JR Z,n00 101 0000x28
JR NC,n00 110 0000x30
JR C,n00 111 0000x38

X=0 and Z=1

Loads and additions of 16 bit registers with immediate short

Mmemonicx y zHex
LD BC,nn00 000 0010x01
ADD HL,BC00 001 0010x09
LD DE,nn00 010 0010x11
ADD HL,DE00 011 0010x19
LD HL,nn00 100 0010x21
ADD HL,HL00 101 0010x29
LD SP,nn00 110 0010x31
ADD HL,SP00 111 0010x39

X=0 and Z=2

Loads using 16 bit registers

Mmemonicx y zHex
LD (BC),A00 000 0100x02
LD A,(BC)00 001 0100x0A
LD (DE),A00 010 0100x12
LD A,(DE)00 011 0100x1A
LD (HL+),A00 100 0100x22
LD A,(HL+)00 101 0100x2A
LD (HL-),A00 110 0100x32
LD A,(HL-)00 111 0100x3A

X=0 and Z=3

Increment/Decrement operations in 16 bit registers

Mmemonicx y zHex
INC BC00 000 0110x03
DEC BC00 001 0110x0B
INC DE00 010 0110x13
DEC DE00 011 0110x1B
INC HL00 100 0110x23
DEC HL00 101 0110x2B
INC SP00 110 0110x33
DEC SP00 111 0110x3B

X=0 and Z=4

Increment operations in 8 bit registers

Mmemonicx y zHex
INC B00 000 1000x04
INC C00 001 1000x0C
INC D00 010 1000x14
INC E00 011 1000x1C
INC H00 100 1000x24
INC L00 101 1000x2C
INC (HL)00 110 1000x34
INC A00 111 1000x3C

X=0 and Z=5

Decrement operations in 8 bit registers

Mmemonicx y zHex
DEC B00 000 1010x05
DEC C00 001 1010x0D
DEC D00 010 1010x15
DEC E00 011 1010x1D
DEC H00 100 1010x25
DEC L00 101 1010x2D
DEC (HL)00 110 1010x35
DEC A00 111 1010x3D

X=0 and Z=6

Load with immediate bytes

Mmemonicx y zHex
LD B,n00 000 1100x06
LD C,n00 001 1100x0E
LD D,n00 010 1100x16
LD E,n00 011 1100x1E
LD H,n00 100 1100x26
LD L,n00 101 1100x2E
LD (HL),n00 110 1100x36
LD A,n00 111 1100x3E

X=0 and Z=7

Mmemonicx y zHex
RLC A00 000 1110x07
RRC A00 001 1110x0F
RL A00 010 1110x17
RR A00 011 1110x1F
DAA00 100 1110x27
CPL00 101 1110x2F
SCF00 110 1110x37
CCF00 111 1110x3F

X=1 and Y=0

LD B,r

Mmemonicx y zHex
LD B,B01 000 0000x40
LD B,C01 000 0010x41
LD B,D01 000 0100x42
LD B,E01 000 0110x43
LD B,H01 000 1000x44
LD B,L01 000 1010x45
LD B,(HL)01 000 1100x46
LD B,A01 000 1110x47

X=1 and Y=1

LD C,r

Mmemonicx y zHex
LD C,B01 001 0000x48
LD C,C01 001 0010x49
LD C,D01 001 0100x4A
LD C,E01 001 0110x4B
LD C,H01 001 1000x4C
LD C,L01 001 1010x4D
LD C,(HL)01 001 1100x4E
LD C,A01 001 1110x4F

X=1 and Y=2

LD D,r

Mmemonicx y zHex
LD D,B01 010 0000x50
LD D,C01 010 0010x51
LD D,D01 010 0100x52
LD D,E01 010 0110x53
LD D,H01 010 1000x54
LD D,L01 010 1010x55
LD D,(HL)01 010 1100x56
LD D,A01 010 1110x57

X=1 and Y=3

LD E,r

Mmemonicx y zHex
LD E,B01 011 0000x58
LD E,C01 011 0010x59
LD E,D01 011 0100x5A
LD E,E01 011 0110x5B
LD E,H01 011 1000x5C
LD E,L01 011 1010x5D
LD E,(HL)01 011 1100x5E
LD E,A01 011 1110x5F

X=1 and Y=4

LD H,r

Mmemonicx y zHex
LD H,B01 100 0000x60
LD H,C01 100 0010x61
LD H,D01 100 0100x62
LD H,E01 100 0110x63
LD H,H01 100 1000x64
LD H,L01 100 1010x65
LD H,(HL)01 100 1100x66
LD H,A01 100 1110x67

X=1 and Y=5

LD L,r

Mmemonicx y zHex
LD L,B01 101 0000x68
LD L,C01 101 0010x69
LD L,D01 101 0100x6A
LD L,E01 101 0110x6B
LD L,H01 101 1000x6C
LD L,L01 101 1010x6D
LD L,(HL)01 101 1100x6E
LD L,A01 101 1110x6F

X=1 and Y=6

LD (HL),r

Mmemonicx y zHex
LD (HL),B01 110 0000x70
LD (HL),C01 110 0010x71
LD (HL),D01 110 0100x72
LD (HL),E01 110 0110x73
LD (HL),H01 110 1000x74
LD (HL),L01 110 1010x75
HALT01 110 1100x76
LD (HL),A01 110 1110x77

X=1 and Y=7

LD A,r

Mmemonicx y zHex
LD A,B01 111 0000x78
LD A,C01 111 0010x79
LD A,D01 111 0100x7A
LD A,E01 111 0110x7B
LD A,H01 111 1000x7C
LD A,L01 111 1010x7D
LD A,(HL)01 111 1100x7E
LD A,A01 111 1110x7F

X=2 and Y=0

Add

Mmemonicx y zHex
ADD A,B10 000 0000x80
ADD A,C10 000 0010x81
ADD A,D10 000 0100x82
ADD A,E10 000 0110x83
ADD A,H10 000 1000x84
ADD A,L10 000 1010x85
ADD A,(HL)10 000 1100x86
ADD A,A10 000 1110x87

X=2 and Y=1

Add with carry

Mmemonicx y zHex
ADC A,B10 001 0000x88
ADC A,C10 001 0010x89
ADC A,D10 001 0100x8A
ADC A,E10 001 0110x8B
ADC A,H10 001 1000x8C
ADC A,L10 001 1010x8D
ADC A,(HL)10 001 1100x8E
ADC A,A10 001 1110x8F

X=2 and Y=2

Subtract

Mmemonicx y zHex
SUB A,B10 010 0000x90
SUB A,C10 010 0010x91
SUB A,D10 010 0100x92
SUB A,E10 010 0110x93
SUB A,H10 010 1000x94
SUB A,L10 010 1010x95
SUB A,(HL)10 010 1100x96
SUB A,A10 010 1110x97

X=2 and Y=3

Subtract with carry

Mmemonicx y zHex
SBC A,B10 011 0000x98
SBC A,C10 011 0010x99
SBC A,D10 011 0100x9A
SBC A,E10 011 0110x9B
SBC A,H10 011 1000x9C
SBC A,L10 011 1010x9D
SBC A,(HL)10 011 1100x9E
SBC A,A10 011 1110x9F

X=2 and Y=4

Bitwise AND

Mmemonicx y zHex
AND A,B10 100 0000xA0
AND A,C10 100 0010xA1
AND A,D10 100 0100xA2
AND A,E10 100 0110xA3
AND A,H10 100 1000xA4
AND A,L10 100 1010xA5
AND A,(HL)10 100 1100xA6
AND A,A10 100 1110xA7

X=2 and Y=5

Bitwise XOR

Mmemonicx y zHex
XOR A,B10 101 0000xA8
XOR A,C10 101 0010xA9
XOR A,D10 101 0100xAA
XOR A,E10 101 0110xAB
XOR A,H10 101 1000xAC
XOR A,L10 101 1010xAD
XOR A,(HL)10 101 1100xAE
XOR A,A10 101 1110xAF

X=2 and Y=6

Bitwise OR

Mmemonicx y zHex
OR A,B10 110 0000xB0
OR A,C10 110 0010xB1
OR A,D10 110 0100xB2
OR A,E10 110 0110xB3
OR A,H10 110 1000xB4
OR A,L10 110 1010xB5
OR A,(HL)10 110 1100xB6
OR A,A10 110 1110xB7

X=2 and Y=7

Compare

Mmemonicx y zHex
CP A,B10 111 0000xB8
CP A,C10 111 0010xB9
CP A,D10 111 0100xBA
CP A,E10 111 0110xBB
CP A,H10 111 1000xBC
CP A,L10 111 1010xBD
CP A,(HL)10 111 1100xBE
CP A,A10 111 1110xBF

X=3 and Z=0

Relative returns, I/O loads and stack manipulation

Mmemonicx y zHex
RET NZ11 000 0000xC0
RET Z11 001 0000xC8
RET NC11 010 0000xD0
RET C11 011 0000xD8
LD (FF00+n),A11 100 0000xE0
ADD SP,d11 101 0000xE8
LD A,(FF00+n)11 110 0000xF0
LDHL SP,d11 111 0000xF8

X=3 and Z=1

Stack pop and absolute returns

Mmemonicx y zHex
POP BC11 000 0010xC1
RET11 001 0010xC9
POP DE11 010 0010xD1
RETI11 011 0010xD9
POP HL11 100 0010xE1
JP (HL)11 101 0010xE9
POP AF11 110 0010xF1
LD SP,HL11 111 0010xF9

X=3 and Z=2

Absolute conditional jumps, I/O load

Mmemonicx y zHex
JP NZ,nn11 000 0100xC2
JP Z,nn11 001 0100xCA
JP NC,nn11 010 0100xD2
JP C,nn11 011 0100xDA
LD (FF00+C),A11 100 0100xE2
LD (nn),A11 101 0100xEA
LD A,(FF00+C)11 110 0100xF2
LD A,(nn)11 111 0100xFA

X=3 and Z=3

Absolute jump, prefix and interrupts

Mmemonicx y zHex
JP nn11 000 0110xC3
PREFIX11 001 0110xCB
XXXX11 010 0110xD3
XXXX11 011 0110xDB
XXXX11 100 0110xE3
XXXX11 101 0110xEB
DI11 110 0110xF3
EI11 111 0110xFB

X=3 and Z=4

Conditional calls

Mmemonicx y zHex
CALL NZ,nn11 000 1000xC4
CALL Z,nn11 001 1000xCC
CALL NC,nn11 010 1000xD4
CALL C,nn11 011 1000xDC
XXXX11 100 1000xE4
XXXX11 101 1000xEC
XXXX11 110 1000xF4
XXXX11 111 1000xFC

X=3 and Z=5

Stack push

Mmemonicx y zHex
PUSH BC11 000 1010xC5
CALL nn11 001 1010xCD
PUSH DE11 010 1010xD5
XXXX11 011 1010xDD
PUSH HL11 100 1010xE5
XXXX11 101 1010xED
PUSH AF11 110 1010xF5
XXXX11 111 1010xFD

X=3 and Z=6

8 bit ALU with immediate byte

Mmemonicx y zHex
ADD A,n11 000 1100xC6
ADC A,n11 001 1100xCE
SUB A,n11 010 1100xD6
SBC A,n11 011 1100xDE
AND A,n11 100 1100xE6
XOR A,n11 101 1100xEE
OR A,n11 110 1100xF6
CP A,n11 111 1100xFE

X=3 and Z=7

Reset table

Mmemonicx y zHex
RST 011 000 1110xC7
RST 811 001 1110xCF
RST 1011 010 1110xD7
RST 1811 011 1110xDF
RST 2011 100 1110xE7
RST 2811 101 1110xEF
RST 3011 110 1110xF7
RST 3811 111 1110xFF